ICS843002I-41规格书应用电路批发供应瑞萨-114ic电子网

型号	下载订购	功能描述	制造商上传企业	LOGO
ICS843002I-41	文件：3.11985 Mbytes Page：23 Pages	700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR 文件：3.11985 Mbytes 页数：23 Pages	IDT	IDT
ICS843002I-41	文件：277.72 Kbytes Page：21 Pages	700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR 文件：277.72 Kbytes 页数：21 Pages	ICST	ICST
843002I-41	文件：550.11 Kbytes Page：25 Pages	700MHZ, FemtoClock® VCXO Based Sonet/SDH Jitter Attenuators General Description The ICS843002I-41 is a PLL based synchronous clock generator that is optimized for SONET/SDH line card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage us 文件：550.11 Kbytes 页数：25 Pages	RENESAS 瑞萨	RENESAS
843002I-41	文件：341.32 Kbytes Page：24 Pages	700MHZ, FemtoClock VCXO Based Sonet/SDH Jitter Attenuators 文件：341.32 Kbytes 页数：24 Pages	IDT	IDT

更多ICS843002I-41供应商更新时间2026-2-3 10:50:00