丝印：830；Package：TO-220；5A 500V N-channel Enhancement Mode Power MOSFET

文件：1.72598 Mbytes 页数：12 Pages

WXDH

东海半导体

丝印：830；Package：TO-220；5A 500V N-channel Enhancement Mode Power MOSFET

文件：1.71139 Mbytes 页数：12 Pages

WXDH

东海半导体

丝印：830B；Package：SMA；1.5W SURFACE MOUNT ZENER DIODE

Glass Passivated Die Construction 1.5W Power Dissipation 3.3V – 200V Nominal Zener Voltage 5% Standard Vz Tolerance Low Inductance For Use in Voltage Regulator or Reference Plastic Case Material has UL Flammability Classification Rating 94V-0

文件：105.77 Kbytes 页数：5 Pages

WTE

Won-Top Electronics

丝印：830B；Package：SMA；1.5 Watt Plastic Surface Mount Zener Voltage Regulators

Features • Standard Zener Breakdown Voltage Range − 3.3 V to 68 V • ESD Rating of Class 3 (> 16 kV) per Human Body Model • Flat Handling Surface for Accurate Placement • Package Design for Top Slide or Bottom Circuit Board Mounting • Low Profile Package • Ideal Replacement for MELF Packages

文件：225.09 Kbytes 页数：6 Pages

ONSEMI

安森美半导体

丝印：83020012A；Package：LCCC；OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

* Eight Latches in a Single Package * 3-State Bus-Driving True Outputs * Full Parallel Access for Loading * Buffered Control Inputs * pnp Inputs Reduce dc Loading on Data Lines description These octal transparent D-type latches feature 3-state outputs designed specifically for driving h

文件：1.43445 Mbytes 页数：24 Pages

TI

德州仪器

丝印：8302001RA；Package：CDIP；OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

* Eight Latches in a Single Package * 3-State Bus-Driving True Outputs * Full Parallel Access for Loading * Buffered Control Inputs * pnp Inputs Reduce dc Loading on Data Lines description These octal transparent D-type latches feature 3-state outputs designed specifically for driving h

文件：1.43445 Mbytes 页数：24 Pages

TI

德州仪器

丝印：8302102RA；Package：CDIP；8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS

Multiplexed I/O Ports Provide Improved Bit Density Four Modes of Operation: − Hold (Store) − Shift Right − Shift Left − Load Data Operate With Outputs Enabled or at High Impedance 3-State Outputs Drive Bus Lines Directly Can Be Cascaded for n-Bit Word Lengths Synchronous Clear Applicat

文件：377.08 Kbytes 页数：13 Pages

TI

德州仪器

丝印：8302102SA；Package：CFP；8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS

Multiplexed I/O Ports Provide Improved Bit Density Four Modes of Operation: − Hold (Store) − Shift Right − Shift Left − Load Data Operate With Outputs Enabled or at High Impedance 3-State Outputs Drive Bus Lines Directly Can Be Cascaded for n-Bit Word Lengths Synchronous Clear Applicat

文件：377.08 Kbytes 页数：13 Pages

TI

德州仪器

丝印：83021AIL；Package：SOIC；1-to-1 Differential-to-LVCMOS/LVTTL Translator

Features • One LVCMOS/LVTTL output • Differential CLK/nCLK input pair • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency: 350MHz (typical) • Part-to-part skew: 500ps (maximum) • Additive phase jitter, RMS: 0.21ps (typical)

文件：513.32 Kbytes 页数：13 Pages

RENESAS

瑞萨

丝印：83021AIL；Package：SOIC；1-to-1 Differential-to-LVCMOS/LVTTL Translator

Features • One LVCMOS/LVTTL output • Differential CLK/nCLK input pair • CLK/nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency: 350MHz (typical) • Part-to-part skew: 500ps (maximum) • Additive phase jitter, RMS: 0.21ps (typical)

文件：513.32 Kbytes 页数：13 Pages

RENESAS

瑞萨