25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Features • 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on C0, C1, and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Available in 96-ball LFBGA pa

文件：818.65 Kbytes 页数：31 Pages

RENESAS

瑞萨

Package：96-LFBGA；包装：管件 类别：集成电路（IC） 专用逻辑器件 描述：IC BUFFER 25BIT CONF DDR2 96BGA

Renesas Electronics America Inc

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive

文件：640.03 Kbytes 页数：31 Pages

IDT

SOT23-5

ST

上传：深圳市向鸿伟业电子有限公司

TSSOP-48

Fairchild

仙童半导体

上传：深圳市创博伟业科技有限公司