丝印：74LS280；Package：SOP；9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Can Be Used to Upgrade Existing Systems using MSI Parity Circuits Typical Data-to-Output Delay of Only 14 ns for “S280 and 33 ns for ‘LS280 Typical Power Dissipation: ‘LS280. ..80 mW ‘S280. . . 335 mW descrip

文件：895.28 Kbytes 页数：21 Pages

TI

德州仪器

丝印：74LS280；Package：SOP；9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Can Be Used to Upgrade Existing Systems using MSI Parity Circuits Typical Data-to-Output Delay of Only 14 ns for “S280 and 33 ns for ‘LS280 Typical Power Dissipation: ‘LS280. ..80 mW ‘S280. . . 335 mW descrip

文件：895.28 Kbytes 页数：21 Pages

TI

德州仪器

丝印：74LS283；Package：SOP；4-BIT BINARY FULL ADDERS WITH FAST CARRY

Full-Carry Look-Ahead Across the Four Bits Systems Achieve Partial Look-Ahead Performance with the Economy of Ripple Carry Supply Voltage and Ground on Corner Pins to Simplify P-C Board Layout description The *283 and 'LS283 adders are electrically and functionally identical to the

文件：441.48 Kbytes 页数：12 Pages

TI

德州仪器

丝印：74LS283；Package：SOP；4-BIT BINARY FULL ADDERS WITH FAST CARRY

Full-Carry Look-Ahead Across the Four Bits Systems Achieve Partial Look-Ahead Performance with the Economy of Ripple Carry Supply Voltage and Ground on Corner Pins to Simplify P-C Board Layout description The *283 and 'LS283 adders are electrically and functionally identical to the

文件：441.48 Kbytes 页数：12 Pages

TI

德州仪器

丝印：74LS373；Package：SOP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件：1.58154 Mbytes 页数：32 Pages

TI

德州仪器

丝印：74LS374；Package：SOP；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件：1.58154 Mbytes 页数：32 Pages

TI

德州仪器

丝印：74LS38；Package：SO；QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS

description These devices contain four independent 2-input NAND buffer gates with open-collector outputs. The open- collector outputs require pull-up resistors to perform correctly. They may be connected to other open- collector outputs to implement active-low wired-OR or active-high wired-A

文件：1.32219 Mbytes 页数：24 Pages

TI

德州仪器

丝印：74LS122；Package：SO；RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

文件：1.44339 Mbytes 页数：26 Pages

TI

德州仪器

丝印：74LS123；Package：SO；RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

文件：1.44339 Mbytes 页数：26 Pages

TI

德州仪器

丝印：74LS123；Package：SO；RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

文件：1.44339 Mbytes 页数：26 Pages

TI

德州仪器