16-Bit Serial/Parallel-In, Serial-Out Shift Register

General Description The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P0–P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal. When M is

文件：57.4 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

16-bit serial/parallel-in, serial-out shift register 3-State

DESCRIPTION The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the mode (M) input is High, information present on the parallel data (D0–D15) inputs is entered on the falling edge of the clock pulse (CP) input signal. When M is Low,

文件：87.95 Kbytes 页数：10 Pages

PHI

PHI

54F676 74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register

文件：431.12 Kbytes 页数：12 Pages

TI

德州仪器

16-Bit Serial/Parallel-In, Serial-Out Shift Register

文件：68.99 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

16-Bit Serial/Parallel-In, Serial-Out Shift Register

ONSEMI

安森美半导体

16-Bit Serial/Parallel-In, Serial-Out Shift Register

General Description The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P0–P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal. When M is

文件：57.4 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

16-Bit Serial/Parallel-In, Serial-Out Shift Register

General Description The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P0–P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal. When M is

文件：57.4 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

16-Bit Serial/Parallel-In, Serial-Out Shift Register

General Description The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P0–P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal. When M is

文件：57.4 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

16-Bit Serial/Parallel-In, Serial-Out Shift Register

文件：68.99 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

16-Bit Serial/Parallel-In, Serial-Out Shift Register

文件：68.99 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体