Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26??Series Resistors in the B-Port Outputs

General Description The 74ALVC162601, 18-bit universal bus transceiver, combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. The 74ALVC162601 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The

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Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26??Series Resistors in the Outputs

General Description The ALVC162827 contains twenty non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is byte controlled. Each byte has NOR output enables for maximum control flexibility. F

文件：77.43 Kbytes 页数：6 Pages

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Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26??Series Resistors in the Outputs

General Description The ALVC162827 contains twenty non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is byte controlled. Each byte has NOR output enables for maximum control flexibility. F

文件：77.43 Kbytes 页数：6 Pages

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18-bit registered driver with inverted register enable and 30ohm termination resistors 3-State

DESCRIPTION The 74ALVC162834A is an 18-bit registered driver. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 12 mA at 3.0 V • MULTIBYTETM flow-through sta

文件：122.75 Kbytes 页数：12 Pages

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18-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state

1 General description The 74ALVC162834A is an 18-bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is

文件：202.15 Kbytes 页数：15 Pages

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18-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state

1 General description The 74ALVC162834A is an 18-bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is

文件：202.15 Kbytes 页数：15 Pages

NEXPERIA

安世

18-bit registered driver with inverted register enable and 30ohm termination resistors 3-State

DESCRIPTION The 74ALVC162834A is an 18-bit registered driver. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 12 mA at 3.0 V • MULTIBYTETM flow-through sta

文件：122.75 Kbytes 页数：12 Pages

PHI

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Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26??Series Resistors in Outputs

General Description The ALVC162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. The ALVC162835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applications suc

文件：89.92 Kbytes 页数：7 Pages

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18-bit registered driver with 30 Ω termination resistors; 3-state

1 General description The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW

文件：201.1 Kbytes 页数：15 Pages

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18-bit registered driver with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH tran

文件：94.29 Kbytes 页数：12 Pages

PHI

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