1 General description

The 74ALVC162834A is an 18-bit registered driver. Data flow is controlled by active low

output enable (OE), active low latch enable (LE) and clock inputs (CP).

When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held

at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is

stored in the latch/flip-flop.

The 74ALVC162834A is designed with 30 Ω series resistors in both HIGH or LOW output

stages.

When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high

impedance OFF-state. Operation of the OE input does not affect the state of the latch/

flip-flop.

To ensure the high-impedance state during power up or power down, OE should be tied

to VCC through a pull-up resistor; the minimum value of the resistor is determined by the

current-sinking capability of the driver.

2 Features and benefits

• Wide supply voltage range from 1.2 V to 3.6 V

• CMOS low-power consumption

• Direct interface with TTL levels (2.7 V to 3.6 V)

• Current drive ± 12 mA at 3.0 V

• MULTIBYTE flow-through standard pin-out architecture

• Low inductance multiple VCC and GND pins for minimum noise and ground bounce

• Output drive capability 50 Ω transmission lines at 85°C

• Integrated 30 Ω termination resistors

• Diode clamps to VCC and GND on all inputs

• Input diodes to accommodate strong drivers

• Complies with JEDEC standard no. 8-1A

74ALVC162834ADGG属于集成电路（IC） > 通用总线功能。安世半导体(中国)有限公司制造生产的74ALVC162834ADGG通用总线功能通用总线功能系列产品是元件级产品，用于处理或操作一系列（通常为 8 个或更多）并行逻辑信号（称为总线）。所执行的功能包括临时存储要发送或接收的数据，执行缓冲以允许输出电流容量有限的器件（例如微处理器）通过远距离互连高速传输数据，以及调换或移动总线内的位顺序等。