Octal D flip-flop with enable

DESCRIPTION The 74ALS377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) is Low. The register is fully edge-triggered. The state of each D input, one setup time before

文件：122.47 Kbytes 页数：10 Pages

PHI

飞利浦

Octal D flip-flop with enable

DESCRIPTION The 74ALS377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) is Low. The register is fully edge-triggered. The state of each D input, one setup time before

文件：122.47 Kbytes 页数：10 Pages

PHI

飞利浦

Octal D flip-flop with enable

DESCRIPTION The 74ALS377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) is Low. The register is fully edge-triggered. The state of each D input, one setup time before

文件：122.47 Kbytes 页数：10 Pages

PHI

飞利浦

Octal D flip-flop with enable

DESCRIPTION The 74ALS377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) is Low. The register is fully edge-triggered. The state of each D input, one setup time before

文件：122.47 Kbytes 页数：10 Pages

PHI

飞利浦