74ALS377DB中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The 74ALS377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) is Low.

The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.

FEATURES

• Ideal for addressable register applications

• Enable for address and data synchronization applications

• Eight edge-triggered D-type flip-flops

• Buffered common clock

• See 74ALS273 for master reset version

• See 74ALS373 for transparent latch version

• See 74ALS374 for 3-State version