8-bit addressable latch

DESCRIPTION The 74AHC/AHCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds

文件：95.93 Kbytes 页数：20 Pages

PHI

飞利浦

8-bit addressable latch

General description The 74AHC259; 74AHCT259 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. Features ■ Balanced propagation delays ■ All inputs have Schmitt-trigger actions ■ Combine

文件：106.09 Kbytes 页数：17 Pages

恩XP

8-bit addressable latch

DESCRIPTION The 74AHC/AHCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds

文件：95.93 Kbytes 页数：20 Pages

PHI

飞利浦

8-bit addressable latch

DESCRIPTION The 74AHC/AHCT259 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds

文件：95.93 Kbytes 页数：20 Pages

PHI

飞利浦