9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS

文件：94.69 Kbytes 页数：7 Pages

TI

德州仪器

9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS

文件：227.29 Kbytes 页数：9 Pages

TI

德州仪器

9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS

文件：227.29 Kbytes 页数：9 Pages

TI

德州仪器

9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS

文件：227.29 Kbytes 页数：9 Pages

TI

德州仪器

9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS

文件：94.69 Kbytes 页数：7 Pages

TI

德州仪器

9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS

文件：227.29 Kbytes 页数：9 Pages

TI

德州仪器

9-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORTS

文件：227.29 Kbytes 页数：9 Pages

TI

德州仪器

具有三态输出的 8 通道、3V 至 5.5V 缓冲器

The 74AC11244 is an octal buffer or line driver designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as two 4-bit buffers or one 8-bit buffer, with active-low output-ena • EPICTM (Enhanced-Performance Implanted CMOS ) 1-um Process \n• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers\n• Flow-Through Architecture Optimizes PCB Layout\n• Center-Pin VCC and GND Pin Configurations Minimize High-Speed Switching Noise\n• 500-mA Typical Latch-Up Immunity a;

TI

德州仪器

八路总线收发器

This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.\nThe device allows noninverted data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the • 3-State Outputs Drive Bus Lines Directly• Flow-Through Architecture Optimizes PCB Layout• Center-Pin VCC and GND Configurations MinimizeHigh-Speed Switching Noise• EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process• 500-mA Typical Latch-Up Immunity at 125°C• Package Options Include Plastic S;

TI

德州仪器

具有三态输出的四路 2 线路到 1 线路数据选择器/多路复用器

This device is designed to multiplex signals from 4-bit data sources to four output data lines in bus-organized systems. The 3-state outputs do not load the data lines when the output-enable (OE\\) input is at a high logic level.\n To ensure the high-impedance state during power up or power down, OE • 3-State Outputs Interface Directly With System Bus\n• Flow-Through Architecture Optimizes PCB Layout\n• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise\n• 500-mA Typical Latch-Up Immunity at 125°C\n• Provides Bus Interface From Multiple Sources in High-Performance Systems;

TI

德州仪器