3.3V 128Kx36 ZBT Synchronous Flow-Through SRAM with 3.3V I/O

The 71V3557 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V3557 contains address, data-in and control si High performance system speed 100 MHz (7.5 ns Clock-to-Data Access)\nZBTTM Feature - No dead cycles between write and read cycles\nInternally synchronized output buffer enable eliminates the need to control OE\nSingle R/W (READ/WRITE) control pin\n4-word burst capability (Interleaved or linear)\nInd;

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Package：119-BGA；包装：托盘 类别：集成电路（IC） 存储器 描述：IC SRAM 4.5MBIT PARALLEL 119PBGA

Renesas Electronics America Inc

Package：119-BGA；包装：托盘 类别：集成电路（IC） 存储器 描述：IC SRAM 4.5MBIT PARALLEL 119PBGA

Renesas Electronics America Inc

Package：119-BGA；包装：托盘 类别：集成电路（IC） 存储器 描述：IC SRAM 4.5MBIT PARALLEL 119PBGA

Renesas Electronics America Inc