3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 2.5V I/O

The 71V2546 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2546 has an on-chip burst counter. In the bu High performance system speed - 150 MHz (3.8 ns Clock-to-Data Access)\nZBTTM Feature - No dead cycles between write and read cycles\nInternally synchronized output buffer enable eliminates the need to control OE\nSingle R/W (READ/WRITE) control pin\nPositive clock-edge triggered address, data, and c;

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128K x 36 3.3V Synchronous ZBT™ SRAM 2.5V I/O, Burst Counter Pipelined Outputs

Features ◆ 128K x 36 memory configurations ◆ Supports high performance system speed - 150 MHz (3.8 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (READ/WRI

文件：279.06 Kbytes 页数：22 Pages

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128K x 36 3.3V Synchronous ZBT™ SRAM 2.5V I/O, Burst Counter Pipelined Outputs

Features ◆ 128K x 36 memory configurations ◆ Supports high performance system speed - 150 MHz (3.8 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (READ/WRI

文件：279.06 Kbytes 页数：22 Pages

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128K x 36 3.3V Synchronous ZBT™ SRAM 2.5V I/O, Burst Counter Pipelined Outputs

Features ◆ 128K x 36 memory configurations ◆ Supports high performance system speed - 150 MHz (3.8 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (READ/WRI

文件：279.06 Kbytes 页数：22 Pages

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128K x 36 3.3V Synchronous ZBT™ SRAM 2.5V I/O, Burst Counter Pipelined Outputs

Features ◆ 128K x 36 memory configurations ◆ Supports high performance system speed - 150 MHz (3.8 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (READ/WRI

文件：279.06 Kbytes 页数：22 Pages

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128K x 36 3.3V Synchronous ZBT™ SRAM 2.5V I/O, Burst Counter Pipelined Outputs

Features ◆ 128K x 36 memory configurations ◆ Supports high performance system speed - 150 MHz (3.8 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (READ/WRI

文件：279.06 Kbytes 页数：22 Pages

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128K x 36 3.3V Synchronous ZBT™ SRAM 2.5V I/O, Burst Counter Pipelined Outputs

Features ◆ 128K x 36 memory configurations ◆ Supports high performance system speed - 150 MHz (3.8 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (READ/WRI

文件：279.06 Kbytes 页数：22 Pages

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瑞萨

128K x 36 3.3V Synchronous ZBT™ SRAM 2.5V I/O, Burst Counter Pipelined Outputs

Features ◆ 128K x 36 memory configurations ◆ Supports high performance system speed - 150 MHz (3.8 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (READ/WRI

文件：279.06 Kbytes 页数：22 Pages

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瑞萨

128K x 36 3.3V Synchronous ZBT™ SRAM 2.5V I/O, Burst Counter Pipelined Outputs

Features ◆ 128K x 36 memory configurations ◆ Supports high performance system speed - 150 MHz (3.8 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (READ/WRI

文件：279.06 Kbytes 页数：22 Pages

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瑞萨

128K x 36 3.3V Synchronous ZBT™ SRAM 2.5V I/O, Burst Counter Pipelined Outputs

Features ◆ 128K x 36 memory configurations ◆ Supports high performance system speed - 150 MHz (3.8 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (READ/WRI

文件：279.06 Kbytes 页数：22 Pages

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