丝印：6004B01L；Package：TSSOP；62.5MHz to 250MHz, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer

FEATURES • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Single LVCMOS/LVTTL clock input • CLK accepts the following input levels: LVCMOS or LVTTL • Output frequency range: 62.5MHz to 250MHz • Input frequency range: 62.5MHz to 250MHz • External feedback for “zero delay” clock rege

文件：155.56 Kbytes 页数：12 Pages

RENESAS

瑞萨

丝印：6004B01L；Package：TSSOP；62.5MHz to 250MHz, 1:4 LVCMOS/ LVTTL Zero Delay Clock Buffer

FEATURES • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Single LVCMOS/LVTTL clock input • CLK accepts the following input levels: LVCMOS or LVTTL • Output frequency range: 62.5MHz to 250MHz • Input frequency range: 62.5MHz to 250MHz • External feedback for “zero delay” clock rege

文件：155.56 Kbytes 页数：12 Pages

RENESAS

瑞萨