86004BG-01LF集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

FEATURES

• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance

• Single LVCMOS/LVTTL clock input

• CLK accepts the following input levels: LVCMOS or LVTTL

• Output frequency range: 62.5MHz to 250MHz

• Input frequency range: 62.5MHz to 250MHz

• External feedback for “zero delay” clock regeneration

with confi gurable frequencies

• Fully integrated PLL

• Cycle-to-cycle jitter, (F_SEL = 1): 45ps (maximum)

• Output skew: 60ps (maximum)

• Supply Voltage Modes:

(Core/Output)

3.3V/3.3V

3.3V/2.5V

2.5V/2.5V

• 5V tolerant input

• -40°C to 70°C ambient operating temperature

• Available in lead-free (RoHS 6) package