2.5V Single Data Rate 1:10 Clock Buffer Terabuffer™ Jr.

FEATURES: • Optimized for 2.5V LVTTL • Guaranteed Low Skew

文件：367.95 Kbytes 页数：10 Pages

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2.5V Differential 1:5 Clock Buffer Terabuffer™

FEATURES: • Guaranteed Low Skew

文件：527.7 Kbytes 页数：22 Pages

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丝印：IDT5T9302EJGI；Package：TSSOP；2.5V LVDS, 1:2 Clock Buffer Terabuffer™II

Features • Guaranteed low skew: 50ps (maximum) • Very low duty cycle distortion: 125ps (maximum) • High speed propagation delay: 1.5ns (maximum) • Up to 450MHz operation • Selectable inputs • Hot insertable and over-voltage tolerant inputs • 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPE

文件：387.49 Kbytes 页数：16 Pages

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丝印：IDT5T9302EJGI；Package：TSSOP；2.5V LVDS, 1:2 Clock Buffer Terabuffer™II

Features • Guaranteed low skew: 50ps (maximum) • Very low duty cycle distortion: 125ps (maximum) • High speed propagation delay: 1.5ns (maximum) • Up to 450MHz operation • Selectable inputs • Hot insertable and over-voltage tolerant inputs • 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPE

文件：387.49 Kbytes 页数：16 Pages

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LVDS, 1:4 Clock Buffer Terabuffer™

Features • Guaranteed low skew: 50ps (maximum) • Very low duty cycle distortion: 125ps (maximum) • Propagation delay: 1.75ns (maximum) • Up to 450MHz operation • Selectable inputs • Hot insertable and over-voltage tolerant inputs • 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL (3.3V)

文件：375.83 Kbytes 页数：17 Pages

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LVDS, 1:4 Clock Buffer Terabuffer™

General Description The 5T9304I differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T9304I can act as

文件：349 Kbytes 页数：18 Pages

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LVDS, 1:4 Clock Buffer Terabuffer™

Features • Guaranteed low skew: 50ps (maximum) • Very low duty cycle distortion: 125ps (maximum) • Propagation delay: 1.75ns (maximum) • Up to 450MHz operation • Selectable inputs • Hot insertable and over-voltage tolerant inputs • 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL (3.3V)

文件：375.83 Kbytes 页数：17 Pages

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2.5V LVDS, 1:2 Glitchless Clock Buffer TERABUFFER™ II

General Description The 5T93GL02 2.5V differential clock buffer is a user-selectable differential input to two LVDS outputs. The fanout from a differential input to two LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T93GL02 can

文件：380.13 Kbytes 页数：18 Pages

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2.5V LVDS, 1:4 Glitchless Clock Buffer TERABUFFER™ II

General Description The 5T93GL04 2.5V differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T93GL04 ca

文件：380.27 Kbytes 页数：18 Pages

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2.5V LVDS, 1:6 Glitchless Clock Buffer TERABUFFER™ II

General Description The 5T93GL06 2.5V differential clock buffer is a user- selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T93GL06 can

文件：408.02 Kbytes 页数：19 Pages

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