LVDS, 1:4 Clock Buffer Terabuffer™

Features • Guaranteed low skew: 50ps (maximum) • Very low duty cycle distortion: 125ps (maximum) • Propagation delay: 1.75ns (maximum) • Up to 450MHz operation • Selectable inputs • Hot insertable and over-voltage tolerant inputs • 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL (3.3V)

文件：375.83 Kbytes 页数：17 Pages

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LVDS, 1:4 Clock Buffer Terabuffer

文件：180.36 Kbytes 页数：16 Pages

IDT

LVDS,1:4 Clock Buffer Terabuffer™

The 5T9304 differential clock buffer has a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T9304 can act as a translator from a differ • Guaranteed low skew: 50ps (maximum)\n• Very low duty cycle distortion: 125ps (maximum)\n• Propagation delay: 1.75ns (maximum)\n• Up to 450MHz operation\n• Selectable inputs\n• Hot insertable and over-voltage tolerant inputs\n• 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML or LVDS;

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LVDS, 1:4 Clock Buffer Terabuffer™

General Description The 5T9304I differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T9304I can act as

文件：349 Kbytes 页数：18 Pages

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瑞萨

LVDS, 1:4 Clock Buffer Terabuffer™

Features • Guaranteed low skew: 50ps (maximum) • Very low duty cycle distortion: 125ps (maximum) • Propagation delay: 1.75ns (maximum) • Up to 450MHz operation • Selectable inputs • Hot insertable and over-voltage tolerant inputs • 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL (3.3V)

文件：375.83 Kbytes 页数：17 Pages

RENESAS

瑞萨

LVDS, 1:4 Clock Buffer Terabuffer

文件：180.36 Kbytes 页数：16 Pages

IDT

LVDS, 1:4 Clock Buffer Terabuffer

文件：153.31 Kbytes 页数：17 Pages

IDT

LVDS, 1:4 Clock Buffer Terabuffer

文件：153.31 Kbytes 页数：17 Pages

IDT

LVDS, 1:4 Clock Buffer Terabuffer

文件：180.36 Kbytes 页数：16 Pages

IDT

LVDS,1:4 Clock Buffer Terabuffer™

The 5T9304I differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T9304I can act as a translator from a diffe • Guaranteed low skew: 50ps (maximum)\n• Propagation delay: 1.75ns (maximum)\n• Selectable inputs\n• 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML or LVDS input interface\n• 2.5V VDD\n• Available in lead-free (RoHS 6) package;

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