54VCXH162373中文资料抗辐照16位D型3态锁存器数据手册ST规格书

描述 Description

The 54VCXH162373 is a low voltage CMOS 16 bit d-type latch with 3 state outputs non inverting fabricated with sub-micron silicon gate and five-layer metal wiring C²MOS technology. It is ideal for low power and very high speed 1.8 to 3.6 V applications; it can be interfaced to 3.6 V signal environment for both inputs and outputs. These 16 bit D-type latches are bite controlled by two latch enable inputs (nLE) and two output enable inputs (OE). While the nLE input is held at a high level, the nQ outputs will follow the data input precisely. When the nLE is taken low, the nQ outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. Bus hold on data inputs is provided in order to eliminate the need for external pull-up or pull-down resistor. The device circuits is including 26 Ω series resistance in the outputs. These resistors permit to reduce line noise in high speed applications. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2 kV ESD immunity and transient excess voltage.

特性 Features

• 1.8 to 3.6 V operating voltage
• High speed:
•tPD= 3.3 ns (Max.) at VCC = 3.0 to 3.6 V
•tPD= 4.5 ns (Max.) at VCC= 2.3 to 2.7 V
• Symmetrical impedance outputs:
•|IOH| = IOL= 12 mA (Min.) at VCC= 3.0 V
•|IOH| = IOL= 8 mA (Min.) at VCC= 2.3 V
• Power down protection on inputs and outputs
• 26 Ω serie resistors in outputs
• Bus hold provided on both sides
• Cold spare function
• 300 krad(Si) Total ionizing dose (TID)
• No SEL, no SEU and no SET at 110 MeV.cm²/mg LET
• QML-V qualified
• SMD 5962F05211
• Mass: 1.50 g