Low Power 8-Bit Latch

TI

德州仪器

Low Power 8-Bit Register

General Description The 100353 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN in

文件：77.27 Kbytes 页数：8 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Low Power 8-Bit Register

General Description The 100353 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN in

文件：77.27 Kbytes 页数：8 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Low Power 8-Bit Register

General Description The 100353 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN in

文件：77.27 Kbytes 页数：8 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司