Data Acquisition System Basis Chip

Features •Two high-precision 24-bit sigma-delta ADCs(18-bit with no missing codes);sample rate: 1Hz to 16kHz •On-chip voltage reference (5ppm/K typical) •Current channel IBAT offset error: ≤ 10mA IBAT resolution: ≤ 1mA Programmable gain: 4 to 512 Max. differential input stage input rang

文件：1.69512 Mbytes 页数：117 Pages

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Data Acquisition System Basis Chip

文件：1.40522 Mbytes 页数：116 Pages

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Data Acquisition System Basis Chip

The ZSSC1750 is a System Basis Chip (SBC) with a dual-channel ADC for battery sensing/management in automotive, industrial, and medical systems. The ZSSC1750 features an SPI interface. One of the two input channels measures the battery current IBAT via the voltage drop at the external shunt resistor Two high-precision 24-bit sigma-delta ADCs (18-bit with no missing codes)\nSample rate: 1Hz to 16kHz\nOn-chip voltage reference (5ppm/K typical)\nCurrent channel IBAT offset error: ≤ 10mA\nCurrent channel IBAT resolution: ≤ 1mA\nCurrent channel programmable gain: 4 to 512\nCurrent channel maximum di;

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瑞萨

Data Acquisition System Basis Chip

Features •Two high-precision 24-bit sigma-delta ADCs(18-bit with no missing codes);sample rate: 1Hz to 16kHz •On-chip voltage reference (5ppm/K typical) •Current channel IBAT offset error: ≤ 10mA IBAT resolution: ≤ 1mA Programmable gain: 4 to 512 Max. differential input stage input rang

文件：1.69512 Mbytes 页数：117 Pages

RENESAS

瑞萨

Data Acquisition System Basis Chip

Features •Two high-precision 24-bit sigma-delta ADCs(18-bit with no missing codes);sample rate: 1Hz to 16kHz •On-chip voltage reference (5ppm/K typical) •Current channel IBAT offset error: ≤ 10mA IBAT resolution: ≤ 1mA Programmable gain: 4 to 512 Max. differential input stage input rang

文件：1.69512 Mbytes 页数：117 Pages

RENESAS

瑞萨

Data Acquisition System Basis Chip

文件：1.40522 Mbytes 页数：116 Pages

IDT