ZL40217中文资料1:6 LVDS Buffer with Input Termination数据手册Microchip规格书

描述 Description

The ZL40217 is an LVDS clock fanout buffer with six output clock drivers capable of operating at frequencies up to 750MHz.The ZL40217 provides an internal input termination network for DC and AC coupled inputs; optional input biasing for AC coupled inputs is also provided. The ZL40217 can accept DC coupled LVPECL or LVDS and AC coupled LVPECL and LVDS input signals, AC coupled CML or HCSL input signals, and single ended signals. A pin compatible device with external termination is also available.The ZL40217 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C.

特性 Features

Low additive jitter of 135 fs RMS
Accepts differential or single-ended input: LVPECL, LVDS, CML, HCSL, LVCMOS
On-chip input termination and biasing for AC coupled inputs
Six precision LVDS outputs. Operating frequency up to 750 MHz
Option for 2.5 V or 3.3 V power supply with current consumption of 97 mA
On-chip Low Drop Out (LDO) Regulator for superior power supply noise rejection

简介

ZL40217属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的ZL40217时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。