ZL30256中文资料3-Channel, 10-In/18-Out Jitter Attenuator数据手册Microchip规格书

描述 Description

CREATE AND SAMPLE YOUR CUSTOM ZL30256 HEREThe ZL30256 is multi-channel high-performance, any-rate multiplier and jitter attenuator which simplifies board design by generating ultra-low-jitter clock signals from or attenuating clock signals while generating additional independent frequency families. With 3 independent jitter attenuating DPLL channels, the ability to create 5 different frequency families and best-in-class jitter performance, the ZL30256 can create complete clock-trees, improving design reliability, reducing bill of materials (BOM) cost, and simplifying design by replacing multiple PLLs and peripheral timing components.

特性 Features

Up to 3 independent DPLL channels
Excellent jitter performance of 180 fs RMS in 12 kHz to 20 MHz band meets jitter requirements of 10G/40G and 100G PHYs
Two programmable ultra-low jitter synthesizers generate any frequency from 1 Hz to 1045 MHz
One programmable general purpose synthesizer generates any clock from 1Hz to 180 MHz
8 differential or 16 single ended (CMOS) ultra-low jitter outputs plus two general purpose CMOS outputs
Accepts up to 10 LVPECL/LVDS/HCSL/LVCMOS inputs
Any input reference can be fed with clock, sync (frame pulse), clock /sync pair or clock modulated with sync pulse (embedded PPS ePPS and embedded PP2S ePP2S)
Up to four programmable digital PLLs/NCOs with loop bandwidth from 14 Hz to 470 Hz synchronize to any clock rate from 1 kHz to 900 MHz and to clock plus sync pulse
Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 1 ppb with post holdover filter
Easy Configuration and dynamic programming via SPI/I2C interface
Operates from a single crystal resonator or clock oscillator

简介

ZL30256属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的ZL30256时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。