丝印：Y4；Package：SOT1089；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：290.66 Kbytes 页数：19 Pages

NEXPERIA

安世

丝印：Y4；Package：SOT1116；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：290.66 Kbytes 页数：19 Pages

NEXPERIA

安世

丝印：Y4；Package：SOT1203；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：290.66 Kbytes 页数：19 Pages

NEXPERIA

安世

丝印：Y4；Package：SOT1116；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：278.15 Kbytes 页数：18 Pages

NEXPERIA

安世

丝印：Y4；Package：SOT1203；Single D-type flip-flop with set and reset; positive edge trigger

1. General description The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transi

文件：278.15 Kbytes 页数：18 Pages

NEXPERIA

安世

丝印：Y4；Package：SOD-523；ZENER DIODE

FEATURES Planar Die Construction 150mW Power Dissipation Zener Voltages from 2.4 – 43V

文件：929.31 Kbytes 页数：5 Pages

SY

顺烨电子

丝印：Y4；Package：SOD-523；ZENER DIODE

Features Constant Voltage Control Wide Voltage Range Selection 2.4V To 75V

文件：258.98 Kbytes 页数：3 Pages

DAESAN

丝印：Y4；Package：SOD-523；SOD-523 Plastic-Encapsulate Zener Diodes

Features Planar Die Construction 150mW Power Dissipation Zener Voltages from 2.4 to 39V

文件：3.22937 Mbytes 页数：7 Pages

UNSEMI

优恩半导体

丝印：Y4；Package：SOT-23；SOT-23 Plastic-Encapsulate Zener Diodes

Features Planar Die Construction 300mW Power Dissipation Zener Voltages from 2.4V to 39V Ultra-Small Surface Mount Package Power Dissipation

文件：3.07656 Mbytes 页数：7 Pages

UNSEMI

优恩半导体

丝印：Y4；Package：SOT-23；Zener Votage Regulator Diodes

GENERAL DATA APPLICABLE TO ALL SERIES IN THISH GROUP Zener Voltage Regulator Diodes MAXIMUM CASE TEMPERATURE FOR SOLDERING PURPOSES: 260°C for 10 seconds

文件：1.10793 Mbytes 页数：4 Pages

SKTECHNOLGYSHIKE Electronics

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