XRK79892中文资料艾科嘉数据手册PDF规格书

GENERAL DESCRIPTION

The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other

three pairs generate 4x, phase aligned clock outputs. External PLL feedback is used to also provide zero

delay buffer performance.

FEATURES

• Fully Integrated PLL

• Intelligent Dynamic Clock Switch

• LVPECL Clock Outputs

• LVCMOS Control I/O

• 3.3V Operation

• 32-Lead LQFP Packagin

• Pin compatible with MPC9892i