INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

GENERAL DESCRIPTION The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequenc

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艾科嘉

INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

GENERAL DESCRIPTION\nThe XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency an • Fully Integrated PLL\n• Intelligent Dynamic Clock Switch\n• LVPECL Clock Outputs\n• LVCMOS Control I/O\n• 3.3V Operation\n• 32-Lead LQFP Packagin\n• Pin compatible with MPC9892i;

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INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

GENERAL DESCRIPTION The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequenc

文件：277.22 Kbytes 页数：10 Pages

EXAR

艾科嘉

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SOP-8

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艾科嘉

上传：深圳市哲瀚电子科技有限公司

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上传：深圳市煦洪科技有限公司