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V62SLASH24609-01XE中文资料德州仪器数据手册PDF规格书

V62SLASH24609-01XE
厂商型号

V62SLASH24609-01XE

功能描述

SN74LV2T74-EP Enhanced Product, Dual D-Type Flip-Flop With Integrated Translation

丝印标识

LV274EP

封装外壳

TSSOP

文件大小

1.05054 Mbytes

页面数量

25

生产厂商 Texas Instruments
企业简称

TI1德州仪器

中文名称

美国德州仪器公司官网

原厂标识
数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-6-22 20:00:00

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V62SLASH24609-01XE规格书详情

1 Features

• Wide operating range of 1.8 V to 5.5 V

• Single-supply voltage translator (refer to LVxT

Enhanced Input Voltage):

– Up translation:

• 1.2 V to 1.8 V

• 1.5 V to 2.5 V

• 1.8 V to 3.3 V

• 3.3 V to 5.0 V

– Down translation:

• 5.0 V, 3.3 V, 2.5 V to 1.8 V

• 5.0 V, 3.3 V to 2.5 V

• 5.0 V to 3.3 V

• 5.5-V tolerant input pins

• Supports standard pinouts

• Up to 150 Mbps with 5-V or 3.3-V VCC

• Latch-up performance exceeds 250 mA

per JESD 17

• Supports defense, aerospace, and medical

applications:

– Controlled baseline

– One assembly and test site

– One fabrication site

– Extended product life cycle

– Product traceability

2 Applications

• Convert a momentary switch to a toggle switch

• Hold a signal during controller reset

• Input slow edge-rate signals

• Operate in noisy environments

• Divide a clock signal by two

3 Description

The SN74LV2T74-EP contains two independent Dtype

positive-edge-triggered flip-flops. A low level at

the preset (PRE) input sets the output high. A low

level at the clear (CLR) input resets the output low.

Preset and clear functions are asynchronous and not

dependent on the levels of the other inputs. When

PRE and CLR are inactive (high), data at the data

(D) input meeting the setup time requirements is

transferred to the outputs (Q, Q) on the positive-going

edge of the clock (CLK) pulse. Clock triggering occurs

at a voltage level and is not directly related to the

rise time of the input clock (CLK) signal. Following

the hold-time interval, data at the data (D) input can

be changed without affecting the levels at the outputs

(Q, Q). The output level is referenced to the supply

voltage (VCC) and supports 1.8-V, 2.5-V, 3.3-V, and

5-V CMOS levels.

The input is designed with a lower threshold circuit to

support up translation for lower voltage CMOS inputs

(for example, 1.2 V input to 1.8 V output or 1.8 V input

to 3.3 V output). In addition, the 5-V tolerant input pins

enable down translation (for example, 3.3 V to 2.5 V

output).

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