128K X 8 STATIC RAM

Description The V62C5181024 is a 1,048,576-bit random-access memory organized as 131,072 words by 8 bits. It is built with MOSEL VITELICs high performance CMOS process. Inputs and tree-state outputs are TTL compatible and allow for circuit interfacing with common system bus structures. Features

文件：59.55 Kbytes 页数：12 Pages

MOSEL

茂矽电子

128K X 8 STATIC RAM

Description The V62C5181024 is a 1,048,576-bit random-access memory organized as 131,072 words by 8 bits. It is built with MOSEL VITELICs high performance CMOS process. Inputs and tree-state outputs are TTL compatible and allow for circuit interfacing with common system bus structures. Features

文件：59.55 Kbytes 页数：12 Pages

MOSEL

茂矽电子

128K X 8 STATIC RAM

Description The V62C5181024 is a 1,048,576-bit random-access memory organized as 131,072 words by 8 bits. It is built with MOSEL VITELICs high performance CMOS process. Inputs and tree-state outputs are TTL compatible and allow for circuit interfacing with common system bus structures. Features

文件：59.55 Kbytes 页数：12 Pages

MOSEL

茂矽电子

128K X 8 STATIC RAM

Description The V62C5181024 is a 1,048,576-bit random-access memory organized as 131,072 words by 8 bits. It is built with MOSEL VITELICs high performance CMOS process. Inputs and tree-state outputs are TTL compatible and allow for circuit interfacing with common system bus structures. Features

文件：59.55 Kbytes 页数：12 Pages

MOSEL

茂矽电子