V53C518165A50中文资料茂矽电子数据手册PDF规格书

Description

The V53C518165A is a 1048576 x 16 bit highperformance CMOS dynamic random access memory. The V53C518165A offers Page mode operation with Extended Data Output. The V53C518165A has symmetric address, 10-bit row and 10-bit column.

All inputs are TTL compatible. EDO Page Mode operation allows random access up to 1024 x 16 bits, within a page, with cycle times as short as 20ns.

These features make the V53C518165A ideally suited for a wide variety of high performance computer systems and peripheral applications.

Features

■ 1MB x 16-bit organization

■ EDO Page Mode for a sustained data rate of 50 MHz

■ RAS access time: 50, 60 ns

■ Dual CAS Inputs

■ Low power dissipation

■ Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh

• Refresh Interval: 1024 cycles/16 ms

■ Available in 42-pin 400 mil SOJ and 44/50-pin 400 mil TSOP-II Packages

■ Single 5V ±10 Power Supply

■ TTL Interface

■ Optional Self Refresh (V53C518165AS)

• Refresh Interval: 1024 cycles/128 ms