UR5596L-S08-T规格书应用电路行情报价友顺-114ic电子网

型号	下载订购	功能描述	制造商上传企业	LOGO
UR5596L-S08-T	文件：202.38 Kbytes Page：11 Pages	MOS IC DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro 文件：202.38 Kbytes 页数：11 Pages	UTC 友顺	UTC
UR5596L-S08-T	文件：219.14 Kbytes Page：12 Pages	DDR TERMINATION REGULATOR 文件：219.14 Kbytes 页数：12 Pages	UTC 友顺	UTC
UR5596L-S08-T	文件：223.86 Kbytes Page：12 Pages	DDR TERMINATION REGULATOR 文件：223.86 Kbytes 页数：12 Pages	UTC 友顺	UTC
UR5596L-S08-R	文件：223.86 Kbytes Page：12 Pages	DDR TERMINATION REGULATOR 文件：223.86 Kbytes 页数：12 Pages	UTC 友顺	UTC
UR5596L-S08-R	文件：219.14 Kbytes Page：12 Pages	DDR TERMINATION REGULATOR 文件：219.14 Kbytes 页数：12 Pages	UTC 友顺	UTC
UR5596L-S08-R	文件：202.38 Kbytes Page：11 Pages	MOS IC DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to pro 文件：202.38 Kbytes 页数：11 Pages	UTC 友顺	UTC

更多UR5596L-S08-T供应商更新时间2025-10-6 16:20:00