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UR5596L-S08-T中文资料友顺数据手册PDF规格书
UR5596L-S08-T规格书详情
DESCRIPTION
The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2(Stub-Series Terminated Logic) specifications for termination of DDR-SDRAM. It also can be used in SSTL-3 or HSTL (High-Speed Transceiver Logic) scheme. The device contains a high-speed OP AMP to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination.
FEATURES
* Source and sink current
* Low output voltage offset
* No external resistors required
* Linear topology
* Suspend To Ram (STR) functionality
* Low external component count
* Thermal shutdown protection
产品属性
- 型号：
UR5596L-S08-T
- 制造商：
UTC-IC
- 制造商全称：
UTC-IC
- 功能描述：
DDR TERMINATION REGULATOR
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
UTC/友顺 |
24+ |
NA/ |
8250 |
原装现货,当天可交货,原型号开票 |
询价 | ||
UTC |
2016+ |
SOP8 |
4262 |
只做原装,假一罚十,公司可开17%增值税发票! |
询价 | ||
UTC/友顺 |
2450+ |
SOP-8 |
8850 |
只做原装正品假一赔十为客户做到零风险!! |
询价 | ||
UTC |
2024+ |
SOP8 |
500000 |
诚信服务,绝对原装原盘 |
询价 | ||
UTC/友顺 |
25+ |
NA |
880000 |
明嘉莱只做原装正品现货 |
询价 | ||
MOT |
25+23+ |
QFP |
39463 |
绝对原装正品全新进口深圳现货 |
询价 | ||
UTC |
WRC7 |
2 |
公司优势库存 热卖中! |
询价 | |||
24+ |
QFP |
147 |
询价 | ||||
ST |
23+ |
DIP2 |
16900 |
正规渠道,只有原装! |
询价 | ||
UTC/友顺 |
24+ |
SOP-8 |
9600 |
原装现货,优势供应,支持实单! |
询价 |
