UPD720101中文资料USB2.0 HOST CONTROLLER数据手册Renesas规格书

描述 Description

The µPD720101 complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The µPD720101 is integrated 3 host controller cores with PCI interface and USB2.0 transceivers into a single chip.FEATURES
• Compliant with Universal Serial Bus Specification Revision 2.0 (Data rate 1.5/12/480 Mbps)
• Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
• Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0
• PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host controller core for high-speed signaling.
• Root hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI host controller cores.
• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction.
• Configurable number of downstream facing ports (2 to 5)
• 32-bit 33 MHz host interface compliant to PCI Specification release 2.2
• Supports PCI Mobile Design Guide Revision 1.1
• Supports PCI-Bus Power Management Interface Specification release 1.1
• PCI bus bus-master access
• System clock is generated by 30 MHz X’tal or 48 MHz clock input.
− System clock frequency should be set from system software (BIOS) or EEPROM. More detail, see µPD720101
User’s Manual.
• Operational registers direct-mapped to PCI memory space
• Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard implementation.
• 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.

特性 Features

• Compliant with Universal Serial Bus Specification Revision 2.0 (Data rate 1.5/12/480 Mbps)
• Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
• Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0
• PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host controller core for high-speed signaling.
• Root hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI host controller cores.
• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction.
• Configurable number of downstream facing ports (2 to 5)
• 32-bit 33 MHz host interface compliant to PCI Specification release 2.2
• Supports PCI Mobile Design Guide Revision 1.1
• Supports PCI-Bus Power Management Interface Specification release 1.1
• PCI bus bus-master access
• System clock is generated by 30 MHz X’tal or 48 MHz clock input.
− System clock frequency should be set from system software (BIOS) or EEPROM. More detail, see µPD720101
User’s Manual.
• Operational registers direct-mapped to PCI memory space
• Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard implementation.
• 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.