128M-bit Synchronous DRAM 4-bank, LVTTL

文件：821.74 Kbytes 页数：86 Pages

ELPIDA

尔必达

128M-bit Synchronous DRAM 4-bank, LVTTL

文件：821.74 Kbytes 页数：86 Pages

ELPIDA

尔必达

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Description\nThe µPD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as 2,097,152 ×16 ×4 (word ×bit ×bank). The synchronous DRAM achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge •Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge\n•Pulsed interface\n•Possible to assert random column address in every cycle\n•Quad internal banks controlled by BA0(A13) and BA1(A12)\n•Byte control by LDQM and UDQM\n•Programmable Wrap sequence (Sequential / Inter;

Micron

美光

128M-bit Synchronous DRAM 4-bank, LVTTL

Micron

美光