UPD45128163G5-A75

128M-bit Synchronous DRAM 4-bank, LVTTL

Description TheµPD45128441,45128841,45128163arehigh-speed134,217,728-bitsynchronousdynamicrandom-accessmemories,organizedas8,388,608×4×4,4,194,304×8×4,2,097,152×16×4(word×bit×bank),respectively. ThesynchronousDRAMsachievedhigh-speeddatatransferusingthepi

UPD45128163G5-A75-9JF

128M-bit Synchronous DRAM 4-bank, LVTTL

Description TheµPD45128441,45128841,45128163arehigh-speed134,217,728-bitsynchronousdynamicrandom-accessmemories,organizedas8,388,608×4×4,4,194,304×8×4,2,097,152×16×4(word×bit×bank),respectively. ThesynchronousDRAMsachievedhigh-speeddatatransferusingthepi

UPD45128163G5-A75I-9JF

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Description TheµPD45128441,45128841,45128163arehigh-speed134,217,728-bitsynchronousdynamicrandom-accessmemories,organizedas8,388,608×4×4,4,194,304×8×4,2,097,152×16×4(word×bit×bank),respectively. ThesynchronousDRAMsachievedhigh-speeddatatransferusingthepi

UPD45128163G5-A75I-9JF-E

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Description TheµPD45128163ishigh-speed134,217,728-bitsynchronousdynamicrandom-accessmemory,organizedas2,097,152×16×4(word×bit×bank).ThesynchronousDRAMachievedhigh-speeddatatransferusingthepipelinearchitecture.Allinputsandoutputsaresynchronizedwiththepositive

UPD45128163G5-A75LI-9JF

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Description TheµPD45128441,45128841,45128163arehigh-speed134,217,728-bitsynchronousdynamicrandom-accessmemories,organizedas8,388,608×4×4,4,194,304×8×4,2,097,152×16×4(word×bit×bank),respectively. ThesynchronousDRAMsachievedhigh-speeddatatransferusingthepi

UPD45128163G5-A75LI-9JF-E

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Description TheµPD45128163ishigh-speed134,217,728-bitsynchronousdynamicrandom-accessmemory,organizedas2,097,152×16×4(word×bit×bank).ThesynchronousDRAMachievedhigh-speeddatatransferusingthepipelinearchitecture.Allinputsandoutputsaresynchronizedwiththepositive

UPD45128163G5-A75LI-9JF-E

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range); •Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge\n•Pulsed interface\n•Possible to assert random column address in every cycle\n•Quad internal banks controlled by BA0(A13) and BA1(A12)\n•Byte control by LDQM and UDQM\n•Programmable Wrap sequence (Sequential / Interleave)\n•Programmable burst length (1, 2, 4, 8 and full page)\n•Programmable /CAS latency (2 and 3)\n•Ambient temperature (TA): −40 to + 85°C\n•Automatic precharge and controlled precharge\n•CBR (Auto) refresh and self refresh\n• ×16 organization\n•Single 3.3 V ±0.3 V power supply\n•LVTTL compatible inputs and outputs\n•4,096 refresh cycles / 64 ms\n•Burst termination by Burst stop command and Precharge command\n•TSOP (II) package with lead free solder (Sn-Bi)\nRoHS compliant;

Description\nThe µPD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as 2,097,152 ×16 ×4 (word ×bit ×bank). The synchronous DRAM achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAM is compatible with Low Voltage TTL (LVTTL).\nThis product is packaged in 54-pin TSOP (II).\n

UPD45128163G5-A75LT-9JF

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Description TheµPD45128441,45128841,45128163arehigh-speed134,217,728-bitsynchronousdynamicrandom-accessmemories,organizedas8,388,608×4×4,4,194,304×8×4,2,097,152×16×4(word×bit×bank),respectively. ThesynchronousDRAMsachievedhigh-speeddatatransferusingthepi

UPD45128163G5-A75T-9JF

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Description TheµPD45128441,45128841,45128163arehigh-speed134,217,728-bitsynchronousdynamicrandom-accessmemories,organizedas8,388,608×4×4,4,194,304×8×4,2,097,152×16×4(word×bit×bank),respectively. ThesynchronousDRAMsachievedhigh-speeddatatransferusingthepi

UPD45128163G5-A75-9JF

128M-bit Synchronous DRAM 4-bank, LVTTL