MOS INTEGRATED CIRCUIT

Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA package (13 x 15) • HSTL interface • PLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports • DDR read or write operation initiated each cycle • Pipelined double

文件：597.36 Kbytes 页数：42 Pages

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36M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (15 x 17) • HSTL interface • PLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports • DDR read or write operation initiated each cycle • Pipelined double data rat

文件：425.18 Kbytes 页数：35 Pages

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SOT563

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上传：深圳市正纳电子有限公司

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HTSSOT16

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上传：深圳市正纳电子有限公司

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HTSSOP16

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上传：深圳市正纳电子有限公司