UPD44165362BF5-E50-EQ3-A中文资料瑞萨数据手册PDF规格书

厂商型号	UPD44165362BF5-E50-EQ3-A
功能描述	18M-BIT QDRTM II SRAM 2-WORD BURST OPERATION
文件大小	464.51 Kbytes
页面数量	37 页
生产厂商	RENESAS
中文名称	瑞萨
网址	网址
数据手册	下载地址一下载地址二到原厂下载
更新时间	2025-10-13 12:00:00
人工找货	UPD44165362BF5-E50-EQ3-A价格和库存，欢迎联系客服免费人工找货

特性 Features

• 1.8 ± 0.1 V power supply

• 165-pin PLASTIC BGA (13 x 15)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports with concurrent transactions

• 100 bus utilization DDR READ and WRITE operation

• Two-tick burst for low DDR transaction size

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time and clock skew matching-clock

and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.

• User programmable impedance output (35 to 70 Ω)

• Fast clock cycle time : 3.3 ns (300 MHz), 3.5 ns (287 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port