UPD16782P中文资料瑞萨数据手册PDF规格书

FEATURES

• Can be driven on 5 V (Dynamic range: 4.3 V, VDD2 = 5.0 V)

• 300/288-output

• fCLK = 15 MHz MAX. (VDD1 = 3.0 V)

• Simultaneous/successive sampling selectable according to pixel array

Simultaneous sampling: Vertical stripe

Successive sampling: Delta array, mosaic array

• Two sample and hold circuits

• Low output deviation between pins (± 20 mV MAX.)

• Stripe, delta, and mosaic pixel arrays supported by internal multiplexer circuit

• Left and right shift selected by R,/L pin

• COG mounting possible