288/300 OUTPUT TFT-LCD SOURCE DRIVER

DESCRIPTION The µ PD16780 is a source driver for TFT-LCDs. The µ PD16780 corresponds only to LCD of Stripe array color filter. The µ PD16780 is constitute a shift register which generates the sampling time, and a sample-and-hold circuit which samples the analog voltage. There are two sample-and-h

文件：86.52 Kbytes 页数：16 Pages

NEC

瑞萨

MOS INTEGRATED CIRCUIT

FEATURES • 5.0 V Drive (Dynamic range 4.6 VP-P, VDD2 = 5.0 V) • 288/300 Output channel • fMAX. = 20 MHz (VDD1 = 3.0 V) • Corresponds only to LCD of Stripe array color filter • Two on-chip sample-and-hold circuits • Small output deviation between pins (deviation between chip pins: ±20 mV MAX.

文件：217.87 Kbytes 页数：18 Pages

RENESAS

瑞萨

288/300 OUTPUT TFT-LCD SOURCE DRIVER

Renesas

瑞萨

MOS INTEGRATED CIRCUIT

FEATURES • 5.0 V Drive (Dynamic range 4.6 VP-P, VDD2 = 5.0 V) • 300 Output channel • fCLK = 20 MHz MAX. (VDD1 = 3.0 V) • 1-phase/3-phase sampling clocks supported • Corresponds only to LCD of Stripe array color filter • Two on-chip sample-and-hold circuits • Small output deviation between p

文件：246.28 Kbytes 页数：18 Pages

RENESAS

瑞萨

MOS INTEGRATED CIRCUIT

FEATURES • 5.0 V Drive (Dynamic range 4.6 VP-P, VDD2 = 5.0 V) • 300 Output channel • fCLK = 20 MHz MAX. (VDD1 = 3.0 V) • 1-phase/3-phase sampling clocks supported • Corresponds only to LCD of Stripe array color filter • Two on-chip sample-and-hold circuits • Small output deviation between p

文件：246.28 Kbytes 页数：18 Pages

RENESAS

瑞萨

MOS INTEGRATED CIRCUIT

FEATURES • 5.0 V Drive (Dynamic range 4.6 VP-P, VDD2 = 5.0 V) • 288/300 Output channel • fMAX. = 20 MHz (VDD1 = 3.0 V) • Corresponds only to LCD of Stripe array color filter • Two on-chip sample-and-hold circuits • Small output deviation between pins (deviation between chip pins: ±20 mV MAX.

文件：217.87 Kbytes 页数：18 Pages

RENESAS

瑞萨

288/300 OUTPUT TFT-LCD SOURCE DRIVER

DESCRIPTION The µ PD16780 is a source driver for TFT-LCDs. The µ PD16780 corresponds only to LCD of Stripe array color filter. The µ PD16780 is constitute a shift register which generates the sampling time, and a sample-and-hold circuit which samples the analog voltage. There are two sample-and-h

文件：86.52 Kbytes 页数：16 Pages

NEC

瑞萨