UPD16641中文资料瑞萨数据手册PDF规格书

FEATURES

• CMOS level input

• 240 outputs

• 6 bits (gray scale data) x 3 dots input

• 64-value output by 11 external power supplies and internal D/A converter

• High-speed data transfer: fCLK = 33 MHz MAX. (internal data transfer speed when VDD1 = 3.0 V)

• Pre-charge-less output buffer

• Level of γ -corrected power supply can be inverted.

• Driver power supply voltage selectable is possible (Vsel = H: 3.3 V, Vsel = L: 5.0 V)

• Output voltage range: 2.8 VP-P MAX. (driver power supply voltage VDD2 = 3.0)

4.3 VP-P MAX. (driver power supply voltage VDD2 = 4.5)

• Loaded with slim TCP