UPD16637中文资料瑞萨数据手册PDF规格书

FEATURES

• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter

• Output dynamic range 12.3 VP-P min. (@ VDD2 = 12.5 V)

• Power supply voltage of driver part = VDD2 = 13.0 ±0.5 V

• CMOS level input

• Input of 6 bits (gradation data) by 6 dots

• High-speed data transfer: fmax. = 55 MHz (internal data transfer speed when operating at 3.0 V)

• Display data inversion function (POL2 terminal.)

• 384 outputs

• Single bank arrangement is possible (loaded with slim TCP)