UPD16342中文资料瑞萨数据手册PDF规格书

FEATURES

• Circuit configuration switched by the IBS pin between three 32-bit bi-directional shift registers and six 16-bit bi-directional shift registers.

• Data control with transfer clock (external) and latch

• High-speed data transfer (fMAX. = 40 MHz MIN. at data latch)

(fMAX. = 25 MHz MIN. at cascade connection)

• High withstand output voltage (80 V, +15/–30 mA MAX.)

• High withstand voltage CMOS structure