UPD16334中文资料瑞萨数据手册PDF规格书

FEATURES

• Selectable by IBS pin; three 32-bit bi-directional shift register circuits

configuration or six 16-bit bi-directional shift register circuits configuration

• Data control with transfer clock (external) and latch

• High-speed data transfer (fmax. = 25 MHz min. at data fetch)

(fmax. = 15 MHz min. at cascade connection)

• High withstand output voltage (80 V, 50 mAMAX.)

• 3.3 V CMOS input interface

• High withstand voltage CMOS structure

• Capable of reversing all driver outputs by PC pin