UJA1168TK中文资料采用微型高速CAN系统基础芯片实现局部联网数据手册恩XP规格书

描述 Description

The UJA1168 is a mini high-speed CAN System Basis Chip (SBC) containing anISO 11898-2/5/6 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply fora microcontroller. It also features a watchdog and a Serial Peripheral Interface (SPI). TheUJA1168 can be operated in very low-current Standby and Sleep modes with bus andlocal wake-up capability and supports ISO 11898-6 compliant CAN partial networking bymeans of a selective wake-up function. The microcontroller supply is switched off in Sleepmode. The UJA1168TK and UJA1168TK/FD versions contain a battery-relatedhigh-voltage output (INH) for controlling an external voltage regulator, while theUJA1168TK/VX and UJA1168TK/VX/FD are equipped with a 5 V sensor supply (VEXT).
A dedicated implementation of the partial networking protocol has been embedded intothe UJA1168/FD variants, UJA1168TK/FD and UJA1168TK/VX/FD. This function is called ‘FD-passive’ and is the ability to ignoreCAN FD frames while waiting for a valid wake-up frame in Sleep/Standby mode. Thisadditional feature of partial networking is the perfect fit for networks that support both CAN FD and standard CAN 2.0 communications. It allows normal CAN controllers that do notneed to communicate CAN FD messages to remain in partial networking Sleep/Standbymode during CAN FD communication without generating bus errors.
The UJA1168 implements the standard CAN physical layer as defined in the currentISO11898 standard (-2, -5 and -6). Pending the release of the updated version ofISO11898 including CAN FD, additional timing parameters defining loop delay symmetryare included. This implementation enables reliable communication in the CAN FD fastphase at data rates up to 2 Mbit/s.
A number of configuration settings are stored in non-volatile memory, allowing the SBC tobe adapted for use in a specific application. This makes it possible to configure thepower-on behavior of the UJA1168 to meet the requirements of different applications.

特性 Features

General
• Loop delay symmetry timing enables reliable communication at data rates up to 2 Mbit/s in the CAN FD fast phase
• Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller supply (V1)
• No ‘false’ wake-ups due to CAN FD frame detection in UJA1168TK/FD and UJA1168TK/VX/FD
• ±8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model (HBM) on the CAN bus pins
• CAN bus pins short-circuit proof to ±58 V
• Very low quiescent current in Standby and Sleep modes with full wake-up capability
• Dark green product (halogen free and Restriction of Hazardous Substances (RoHS) compliant)
• 5 V nominal output; ±2 % accuracy
• Current limiting above 150 mA
• Support for microcontroller RAM retention down to a battery voltage of 2 V
• Excellent transient response with a 4.7 μF ceramic output capacitor
• Turned off in Sleep mode
• Standby mode featuring very low supply current; voltage V1 remains active to maintain the supply to the microcontroller
• Remote wake-up capability via standard CAN wake-up pattern or via ISO 11898-6 compliant selective wake-up frame detection
• Wake-up source recognition
• High-voltage output (INH) for controlling an external voltage (UJA1168TK and UJA1168TK/FD)
• Mode control via the Serial Peripheral Interface (SPI)
• Watchdog with independent clock source
• Optional cyclic wake-up in watchdog Timeout mode
• Watchdog period selectable between 8 ms and 4 s
• 16-, 24- and 32-bit SPI for configuration, control and diagnosis
• Configuration of selected functions via non-volatile memory
• 5 V nominal output; ±2 % accuracy
• Current limiting above 30 mA
• Protected against short-circuits to GND and to the battery
• Can handle negative voltages as low as -18 V