7−STAGE RIPPLE COUNTER BINARY COUNTER / DIVIDERS

The UTC UCD4024B is a 7−stage ripple counter with shortpropagation delays and high maximum clock rates. The Reset inputhas standard noise immunity, however the Clock input hasincreased noise immunity due to Hysteresis. The output of eachcounter stage is buffered. Diode Protection on All Inputs Output Transitions Occur on the Falling Edge of the Clock Pulse Supply Voltage Range = 3.0V to 18V Capable of Driving Two Low−power TTL Loads or On Low−power Schottky   TTL Load Over the Rated Temperature Range;

UTC

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