U74LVC126A数据手册UTC中文资料规格书

描述 Description

The U74LVC126A are quadruple bus buffer gates featuringindependent line drivers with 3-state outputs. When OE is low, thenY outputs are in a high-impedance state. When OE is high, thedevice passes non-inverted data from the nA input to its nY output.To ensure the high-impedance state during power up or powerdown, OE should be tied to GND through a pull-down resistor; theminimum value of the resistor is determined by the current-sinkingcapability of the driver.Inputs can be driven from either 3.3V to 5V devices. This featureallows the use of these devices as translators in a mixed 3.3V/5Vsystem environment.

特性 Features

1.65V to 3.6V VCC Operation Max tPD of 4.7ns from A to Y at VCC = 3.3V, CL = 50pF, RL = 500Ω ±24mA output driver at 3V