TMS320LC203中文资料C20x 定点 DSP数据手册TI规格书

描述 Description

The TMS320C2xx generation of digital signal processors (DSPs) combines strong performance and great flexibility to meet the needs of signal processing and control applications. The T320C2xLP core CPU that is the basis of all 'C2xx devices has been optimized for high speed, small size, and low-power, making it ideal for demanding applications in many markets. The CPU has an advanced, modified Harvard architecture with six internal buses that permits tremendous parallelism and data throughput. The powerful 'C2xx instruction set makes software development easy. And because the 'C2xx is code-compatible with the TMS320C2x and 'C5x generations, your code investment is preserved. Around this core, 'C2xx-generation devices feature various combinations of on-chip memory and peripherals. The serial ports provide easy communication with external devices such as codecs, A/D converters, and other processors. Other peripherals that facilitate the control of external devices include general-purpose I/O pins, a 20-bit timer, and a wait-state generator.Because of their strong performance, low cost, and easy-to-use development environment, 'C2xx-generation DSPs are an ideal choice for applications such as smart phones, digital cameras, modems, remote metering, and security systems.Table 2 provides a comparison of the devices in the 'C2xx generation. It shows the capacity of on-chip RAM and ROM, the number of serial and parallel I/O ports, the execution time of one machine cycle, and the type of package with total pin count.Core power dissipation. For complete details, seeCalculation of TMS320C2xx Power Dissipation (literature number SPRA088).

特性 Features

• Based Upon the T320C2xLP Core CPU
• Six Internal Buses for Increased Parallelism and Performance
• 16 × 16-Bit Single-Cycle Multiplier With a 32-Bit Product
• Hardware Repeat Instruction
• Instruction Cycle Time
• 50 ns @ 5 V 50 ns @ 3.3 V 50 ns @ 5 V
• 25 ns @ 5 V
• Upwardly Code-Compatible With TMS320C5x Devices
• Boot-Loader Option ('C203 Only)
• 544 × 16 Words of On-Chip Dual-Access Data RAM
• 4K × 16 Words of On-Chip Program ROM ('C209 Only)
• 224K × 16-Bit Total Addressable External Memory Space
• 64K Data
• 32K Global
• TMS320C2xx Peripherals:
• - ×1, ×2, ×4, 2 ('C203)
• On-Chip Oscillator
• 0 - 7 Wait States Software-Programmable to Each Space ('C203 Only)
• On-Chip 20-Bit Timer
• One Synchronous Serial Port With Four-Level-Deep FIFOs ('C203 Only)
• Supports Hardware Wait States
• Fully Static CMOS Technology
• 1.1 mA/MIPS at 3.3 V
• Up to 40-MIPS Performance at 5 V ('C203)
• HOLD Mode for Multiprocessor Applications
• 80- and 100-pin Small Thin Quad Flat Packages (TQFPs), (PN and PZ Suffixes) IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port.