SMARTDM™ Low-Power, Low-Voltage, 1.1-V to 3.6-V 1/0, 16-Bit, 26-KSPS Codec

1.1 Description The TLV320AIC13 implements the smart time division multiplexed serial port (SMARTDM). This design innovation optimizes the DSP performance with an advanced synchronous serial port in TDM format for glue-free interface to popular DSPs (i.e., C5x, C6x) and microcontrollers. The S

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TI

德州仪器

Low Power CMOS, 16-Bit, 26-KSPS Codec With Smart Time Division Multiplexed (SMARTDM™) Serial Port

1.1 Description The TLV320AIC14 implements the smart time division multiplexed serial port (SMARTDM). This is TI’s design innovation to optimize DSP performance with its most advanced synchronous serial port in TDM format for glue-free interface to popular DSPs (i.e., C5x, C6x) and microcontro

文件：728.04 Kbytes 页数：58 Pages

TI

德州仪器

SMARTDM™ Low-Power, Low-Voltage, 1.1-V to 3.6-V 1/0, 16-Bit, 26-KSPS Codec

1.1 Description The TLV320AIC15 implements the smart time division multiplexed serial port (SMARTDM). This is TI’s design innovation to optimize DSP performance with its most advanced synchronous serial port in TDM format for glue-free interface to popular DSPs (i.e., C5x, C6x) and microcontro

文件：684.32 Kbytes 页数：56 Pages

TI

德州仪器

LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO CODEC

FEATURES · Mono 16-Bit Oversampling Sigma-Delta A/D Converter · Mono 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow the DSP Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Samplin

文件：2.12866 Mbytes 页数：66 Pages

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PRODUCT NOTIFICATION

文件：330.63 Kbytes 页数：50 Pages

TI

德州仪器

LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO CODEC

文件：1.15972 Mbytes 页数：63 Pages

TI

德州仪器

低功耗单声道语音频带编解码器

The TLV320AIC1x is a true low-cost, low-power, high-integrated, high-performance, mono voice codec. It features one 16-bit analog-to-digital (A/D) channel and one 16-bit digital-to-analog (D/A) channel. The TLV320AIC1x provides high-resolution signal conversion from digital-to-analog (D/A) and from • Mono 16-Bit Oversampling Sigma-Delta A/D Converter\n• Support Maximum Master Clock of 100 MHz to Allow the DSP Output Clock to be Used as a Master Clock\n• Programmable Sampling Rate up to: \n• Max 104 Ksps With IIR/FIR Bypassed\n• On-Chip FIR Produced 84-dB SNR for ADC and 92-dB SNR for DAC\n• Gl;

TI

德州仪器

丝印：320AIC12C；Package：TSSOP(DBT)；LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO CODEC

FEATURES · Mono 16-Bit Oversampling Sigma-Delta A/D Converter · Mono 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow the DSP Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Samplin

文件：2.12866 Mbytes 页数：66 Pages

TI

德州仪器

丝印：320AIC12C；Package：TSSOP(DBT)；LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO CODEC

FEATURES · Mono 16-Bit Oversampling Sigma-Delta A/D Converter · Mono 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow the DSP Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Samplin

文件：2.12866 Mbytes 页数：66 Pages

TI

德州仪器

丝印：320AIC12I；Package：TSSOP(DBT)；LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE 16-Bit, 26-KSPS MONO CODEC

FEATURES · Mono 16-Bit Oversampling Sigma-Delta A/D Converter · Mono 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow the DSP Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Samplin

文件：2.12866 Mbytes 页数：66 Pages

TI

德州仪器