首页 >TFP7433PZP>规格书列表
| 零件编号 | 下载 订购 | 功能描述/丝印 | 制造商 上传企业 | LOGO |
|---|---|---|---|---|
Quad2-InputORGate | FairchildFairchild Semiconductor 仙童半导体飞兆/仙童半导体公司 | Fairchild | ||
P-Channel30-VMOSFET | ACE ACE Technology Co., LTD. | ACE | ||
P-Channel30-V(D-S)MOSFET | AnalogPower Analog Power | AnalogPower | ||
20GActiveMux(2x2)withIntegratedRe-timerandCCDetectionforUSB3.2 Features Built-inre-timer −Integratedre-timerforUSB3.2uptoGen2@2x10Gbpsforacombined20Gdatathroughput −SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification(Appendix-E) −Supportsbothhost(source | ANALOGIXAnalogix Semiconductor, Inc. 硅谷数模硅谷数模半导体有限公司 | ANALOGIX | ||
10GActiveMux(1x2)withIntegratedRe-timerforUSB3.2 Features *Built-inre-timer ㅡIntegratedre-timerforUSB3.2uptoGen2@10Gbps —SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification(Appendix-E) —Supportsbothhost(source)anddevice(sink)applicationsinUS | ANALOGIXAnalogix Semiconductor, Inc. 硅谷数模硅谷数模半导体有限公司 | ANALOGIX | ||
20GActiveRetimerforUSB3.2 Features Built-inre-timer -Integratedre-timerforUSB3.2withtwolanesuptoGen2@10Gbpseachforacombined20Gthroughput -SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification -Supportsbothhost(source) | ANALOGIXAnalogix Semiconductor, Inc. 硅谷数模硅谷数模半导体有限公司 | ANALOGIX | ||
106ActiveMux(6x4)withIntegratedRe-timersforUSB3.2/DisplayPort1.4 Features *Built-inre-timers —Integratedre-timersforUSB3.2uptoGen2@10Gbps —SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification(Appendix-E) —Integratedre-timers(Linktraining-tunablePHYrepeater)forD | ANALOGIXAnalogix Semiconductor, Inc. 硅谷数模硅谷数模半导体有限公司 | ANALOGIX | ||
10GActiveMux(4x4)withIntegratedRe-timersforUSB3.2/DisplayPort™ Features Built-inre-timers −Integratedre-timersforUSB3.2uptoGen2@10Gbps −US3.2Specification(Appendix-E)compliantre-timer −SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification(Appendix-E) −Integrat | ANALOGIXAnalogix Semiconductor, Inc. 硅谷数模硅谷数模半导体有限公司 | ANALOGIX | ||
12GActiveRedriverwithLinearEqualizationforHDMI2.1 Features Built-inCTLEredrivers -Independentchannelconfiguration -Losscompensationtorecoverupto-12dBchannelloss@12Gbps FourlanesofHDMI2.1upto12Gbps -SupportsDP++ Serialanddebuginterfaces -I2CSlaveinterface,upto1MHz,forredriverconfiguration Indust | ANALOGIXAnalogix Semiconductor, Inc. 硅谷数模硅谷数模半导体有限公司 | ANALOGIX | ||
BidirectionalActiveUSB-C™CableforUSB3.2(10G)andDP1.3(8.1G) Features BidirectionalactiveUSB-Ccablecarrying4LDPor2LDPandUSB3.2 -Supportsupto4LofDisplayPortin/out,withsignalconditioningupto8.1Gbps(supportsHBR3,HBR2,HBR,RBRrates) -SupportsUSB3.1in/out,withsignalconditioningupto10Gbps -SupportsUSB2.0(480Mbps) - | ANALOGIXAnalogix Semiconductor, Inc. 硅谷数模硅谷数模半导体有限公司 | ANALOGIX |
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