TDRV020-SW-25中文资料TEWS数据手册PDF规格书

Application Information

The TMPE623 is a standard full PCI Express Mini Card, providing a user programmable Xilinx Artix-7 7A50T FPGA.

Depending on the order option the TMPE623 offers 26 ESD-protected 5V-tolerant TTL lines or 13 differential I/O lines using ESD-protected EIA-422 / EIA-485 compatible line transceivers or Multipoint-LVDS transceivers.

All I/O lines are individually programmable as input or output. TTL I/O lines can be set to high, low, or tristate. Each TTL I/O line has a pull-resistor to a common programmable pull voltage that can be set so +3.3 V, +5 V and GND. Differential I/O lines are terminated, EIA-422 / EIA-485 lines with 120 Ω, M-LVDS lines with 100 Ω.

The I/O signals are accessible through a 30 pin Pico-Clasp latching connector.

The User FPGA is configured by a SPI flash. An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design (using Xilinx “ChipScope”). For direct JTAG access to the FPGA using the Xilinx Platform Cable USB, the TA308 Programming Kit is required.

User applications for the TMPE623 with XC7A50T-2 FPGA can be developed using the design software Vivado WebPACK which can be downloaded free of charge from www.xilinx.com.

TEWS offers a well-documented basic FPGA Example Application design. It includes an .xdc file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the TMPE623. It implements local Bus interface to local Bridge device, register mapping and basic I/O. It comes as a Xilinx Vivado project with source code and as a ready-to-download bit stream.

The TMPE623 provides a basic heatsink to facilitate thermal management. The heatsink can be used to install additional cooling solutions like passive or active heatsinks or to provide a thermal connection to an enclosure