TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0

1 Features Processor cores: • Two C7x floating point, vector DSP, up to 1.0 GHz, 160 GFLOPS, 512 GOPS • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist acceler

文件：5.00915 Mbytes 页数：251 Pages

TI

德州仪器

TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0

1 Features Processor cores: • Two C7x floating point, vector DSP, up to 1.0 GHz, 160 GFLOPS, 512 GOPS • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist acceler

文件：5.00915 Mbytes 页数：251 Pages

TI

德州仪器

丝印：TDA4AL88；Package：FCBGA；TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0

1 Features Processor cores: • Two C7x floating point, vector DSP, up to 1.0 GHz, 160 GFLOPS, 512 GOPS • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist acceler

文件：5.00915 Mbytes 页数：251 Pages

TI

德州仪器

TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0

1 Features Processor cores: • Two C7x floating point, vector DSP, up to 1.0 GHz, 160 GFLOPS, 512 GOPS • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist acceler

文件：5.00915 Mbytes 页数：251 Pages

TI

德州仪器

通过摄像头和雷达传感器实现前置摄像头和 ADAS 域控制的汽车片上系统

The TDA4VE TDA4AL TDA4VL processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The TDA4AL provides high performance compu Processor cores: \n• Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz\n• Depth and Motion Processing Accelerators (DMPAC)\n• 1MB shared L2 cache per dual-core Cortex-A72 cluster\n• Up to Six Arm Cortex-R5F MCUs at up to 1.0 GHz \n• Two Arm Cortex-R5F MCUs in isolated MC;

TI

德州仪器