CMOS Digital Integrated Circuit Silicon Monolithic

Features ● DSI-TX Interface  MIPI DSI compliant (Version 1.02.00– June 28, 2010) - Support DSI Video Mode data transfer - DCSSM Command for panel register access  Supports up to 1 Gbps per data lane  Supports1, 2, 3 or 4 data lanes  Supports video data formats - RGB888/666/565 ● RGB

文件：415.6 Kbytes 页数：19 Pages

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CMOS Digital Integrated Circuit Silicon Monolithic

Features ● TC358770AXBG / TC358777XBG follows the following standards:  MIPI® DSISM version 1.02, Jan 2010.  MIPI® D-PHYSM version 1.0, May 2009.  VESA® DisplayPortTM Standard version 1.1a, Jan. 11 2008.  Digital Content Protection LLC, HDCP version 1.3 with DisplayPortTM amendment rev

文件：469.98 Kbytes 页数：21 Pages

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CMOS Digital Integrated Circuit Silicon Monolithic

Features ● DSI Receiver  Configurable 1- up to 4-Data-Lane DSI Link with bi-directional support on Data Lane 0  Maximum bit rate of 1 Gbps/lane  Video input data formats: - RGB565 16 bits per pixel - RGB666 18 bits per pixel - RGB666 loosely packed 24 bits per pixel - RGB888 24 bits pe

文件：393.82 Kbytes 页数：21 Pages

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CMOS Digital Integrated Circuit Silicon Monolithic

Features ● DSI Receiver  Configurable 1- up to 4-Data-Lane DSI Link with bi-directional support on Data Lane 0  Maximum bit rate of 1 Gbps/lane  Video input data formats: - RGB565 16 bits per pixel - RGB666 18 bits per pixel - RGB666 loosely packed 24 bits per pixel - RGB888 24 bits pe

文件：393.82 Kbytes 页数：21 Pages

TOSHIBA

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CMOS Digital Integrated Circuit Silicon Monolithic

Features ● DSI Receiver  Configurable 1- up to 4-Data-Lane DSI Link with bi-directional support on Data Lane 0  Maximum bit rate of 1 Gbps/lane  Video input data formats: - RGB565 16-bits per pixel - RGB666 18-bits per pixel - RGB666 loosely packed 24-bits per pixel - RGB888 24-bits pe

文件：398.25 Kbytes 页数：24 Pages

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东芝

CMOS Digital Integrated Circuit Silicon Monolithic

Features ● DSI Receiver  Configurable 1- up to 4-Data-Lane DSI Link with bi-directional support on Data Lane 0  Maximum bit rate of 1 Gbps/lane  Video input data formats: - RGB565 16-bits per pixel - RGB666 18-bits per pixel - RGB666 loosely packed 24-bits per pixel - RGB888 24-bits pe

文件：398.25 Kbytes 页数：24 Pages

TOSHIBA

东芝

CMOS Digital Integrated Circuit Silicon Monolithic

Features ● TC358770AXBG / TC358777XBG follows the following standards:  MIPI® DSISM version 1.02, Jan 2010.  MIPI® D-PHYSM version 1.0, May 2009.  VESA® DisplayPortTM Standard version 1.1a, Jan. 11 2008.  Digital Content Protection LLC, HDCP version 1.3 with DisplayPortTM amendment rev

文件：469.98 Kbytes 页数：21 Pages

TOSHIBA

东芝

CMOS Digital Integrated Circuit Silicon Monolithic

Features ● DSI-TX Interface  MIPI DSI compliant (Version 1.02.00– June 28, 2010) - Support DSI Video Mode data transfer - DCSSM Command for panel register access  Supports up to 1 Gbps per data lane  Supports1, 2, 3 or 4 data lanes  Supports video data formats - RGB888/666/565 ● RGB

文件：415.6 Kbytes 页数：19 Pages

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CMOS Digital Integrated Circuit Silicon Monolithic

Features ● HDMI-RX Interface  HDMI® 1.4b - Video Formats Support (Up to 1080P @60fps)  RGB, YCbCr444: 24-bpp @60fps  YCbCr422 24-bpp @60fps - Audio Supports  Internal Audio PLL to track N/CTS value transmitted by the ACR packet. - 3D Support - HDCP1.3 Support (optional) - EDID Suppo

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CMOS Digital Integrated Circuit Silicon Monolithic

Features ● HDMI-RX Interface  HDMI 1.4b - Video Formats Support (Up to 4K×2K / 30fps), maximum 24 bps (bit-per-pixel) no deep color support  RGB, YCbCr444: 24-bpp  YCbCr422: 24-bpp - Color Conversion  4:2:2 to 4:4:4 is supported  4:4:4: to 4:2:2 is supported  RGB888 to YCbCr (4:4:

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